1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to semiconductor die conductor structures and to methods of making the same.
2. Description of the Related Art
Conventional integrated circuits are frequently implemented on a semiconductor substrate or die that consists of a small rectangular piece of semiconductor material, typically silicon, fashioned with two opposing principal sides. The active circuitry for the die is concentrated near one of the two principal sides. The side housing the active circuitry is usually termed the “active circuitry side,” while the side opposite the active circuitry side is often referred to as the “bulk silicon side.” Depending on the thermal output of the die, it may be desirable to mount a heat transfer device, such as a heat sink, on the bulk silicon side of the die. This mounting may be directly on the bulk silicon side or on a lid that is positioned over the die.
A conventional die is usually mounted on some form of substrate, such as a package substrate or a printed circuit board. Electrical conductivity between the die and the underlying substrate or board is established through a variety of conventional mechanisms. In a so-called flip-chip configuration, the active circuitry side of the die is provided with a plurality of conductor balls or bumps that are designed to establish a metallurgical bond with a corresponding plurality of conductor pads positioned on the substrate or circuit board. The die is flipped over and seated on the underlying substrate with the active circuitry side facing downwards. A subsequent thermal process is performed to establish the requisite metallurgical bond between the bumps and the pads. One of the principal advantages of a flip-chip mounting strategy is the relatively short electrical pathways between the integrated circuit and the substrate. These relatively low inductance pathways yield a high speed performance for the electronic device.
The manner in which the solder balls are electrically connected to the bond pads of the semiconductor die may have a significant impact on the reliability of semiconductor die and the host electronic device to which it is mounted. In one conventional technique, a dielectric passivation layer is fabricated on the active circuitry side of the semiconductor die and lithographically patterned with a plurality of openings corresponding to the locations of the bond pads. Next, a polyimide layer is fabricated over the passivation layer and lithographically patterned with a plurality of openings that are generally concentrically positioned relative to the openings in the passivation layer. A so-called under bump metallization layer is next deposited over the polyimide layer so that metal extends down to and bonds with the underlying bond pads. Thus, the polyimide layer is positioned between the under bump metal layer and the passivation layer. The significance of this arrangement will be explained in further detail below. After the under bump metallization layer is formed, a film or stencil is patterned on the under bump metal layer with a plurality of openings that are positioned over the general locations of the bond pads and a solder material is deposited by a plating or stencil paste process. The stencil is removed and a thermal process is performed to reflow the solder structures. The solder structures solidify into ball-like structures.
Lead-based solders have been widely used in semiconductor device fabrication for decades. More recently, however, chip manufacturers have begun turning to lead-free solders. Lead-free solder materials tend to have relatively lower ductility than lead-based solders. This increased stiffness can lead to significant stresses in the solder balls, particularly where operating temperatures are high or where there is a significant mismatch between the coefficients of thermal expansion between the semiconductor die and the substrate upon which it is mounted. The difficulty with the conventional technique stems from the relative positions of the polyimide layer, the under bump metallization layer and the solder balls. Because the polyimide layer is essentially separated from the solder balls by the under bump metallization layer, the stress reducing abilities of the polyimide layer are not available to the solder balls. Accordingly, high mechanical stresses may be inflicted on the solder balls, particularly at the edges of the solder balls near the interfaces with the under bump metallization layer. The stresses can lead to cracks in the solders balls. If the stresses are acute enough, mechanical failure of the solder balls can occur and produce electrical device failure.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.